The present invention relates to a static type memory circuit having a stand-by mode, or "Data Retention Mode", for allowing stored information to be maintained by a back-up voltage of a smaller voltage value than a normal operation power voltage, and more particularly, to a memory circuit of the mentioned type having means for detecting reduction in a power supply voltage.
As is well known, a static type memory can operate at a high speed, but it requires a relatively large amount of power consumption. In this point of view, when a memory is not accessed from the outside, a value of the power supply voltage applied to the memory is reduced to a value which is enough to maintain information storage in memory cells but is not enough to perform write and read operations to and from the memory cells, introducing "Data Retention Mode" to the memory. The Data Retention Mode is initiated by turning a chip selection signal applied to the memory chip to an inactive level for disenabling peripheral circuits of the memory cell array such as decoder circuits and a read/ write circuit, and by reducing the power voltage. Recently, such a memory has been proposed that is forced to be switched over into the Data Retention Mode even if the chip selection signal is in an active level, when the value of the power supply voltage drops down to a value equal to or near the value to which the power supply voltage is intentionally reduced in the Data Retention Mode. Such a forced Data Retention Mode is called as "Auto Data Retention Mode". The memory is provided with a voltage value detection circuit for detecting a drop in the power supply voltage for the Auto Data Retention Mode, and with a control circuit responsive to the chip selection signal and to the output of the voltage value detection circuit. With these circuits, even if the chip selection signal is in the active level, the state of the memory can be shifted to the Data Retention Mode by intentionally reducing the power voltage and the peripheral circuits are disenabled, thus enhancing the flexibility in controlling the memory. When the power voltage unintentionally drops, the peripheral circuits are automatically disabled by the Auto Data Retention Mode to protect the stored information. The voltage value detection circuit in the prior art memory comprises a voltage divider circuit composed of resistors serially connected between the power voltage and a reference voltage for dividing the power voltage and of an inverter circuit receiving the output of the voltage divider circuit and logically distinguishing the value of the power voltage between the normal operation mode and Data Retention Mode. The output of the inverter of the voltage value detection circuit is then applied to one input terminal of a NOR gate which receives the chip selection signal at the other input terminal. The NOR gate produces an internal chip selection signal for directly controlling the peripheral circuits. In this prior art voltage value detection circuit, however, a current always flows through the serially connected resistors both in the normal operation mode and in the Data Retention Mode, and therefore a considerable amount of power is inevitably consumed. This problem is more serious in the Data Retention Mode, because a battery is generally used as a back-up voltage source and its capacity is limited.
Furthermore, a relatively large number of circuit elements are required to generate the internal chip selection signal in the mentioned prior art.
It is an object of the present invention to provide memory circuit operable with a low power consumption both in the normal operation mode and in the Data Retention Mode.
It is another object of the present invention to provide a memory circuit which can be fabricated with high-density on a semiconductor chip.
It is still another object of the present invention to provide an improved mode control circuit for controlling operation modes of a memory.